1. Field of the Invention
This invention relates to full width scanning arrays, and more particularly to a method for fabricating coplanar full width scanning arrays from a plurality of relatively short scanning subunits placed into precision end-to-end relationship even though some of the subunits may have different thickness.
2. Description of the Prior Art
It is well known in the raster scanning industry to assemble pagewidth raster input scanning (RIS) and raster output scanning (ROS) bars from relatively short RIS/ROS subunits placed end-to-end. Once assembled, the pagewidth RIS/ROS bars or scanning arrays have the requisite length and number of image processing elements to scan an entire line of information at once with a high image resolution. The subunits have either image reading arrays which comprise a succession of image sensing elements to convert the image line into electrical signals or pixels or image writing arrays which comprise a succession of light producing or other elements employed to produce images in response to an image signal or pixel input.
The prior art has failed to provide a means for fabricating a pagewidth scanning or imaging array from subunits which has adequate precise alignment tolerance in X, Y, and .THETA. space and which is commercially (i.e. economically) feasible. Further, the prior art has failed to provide such a pagewidth scanning array when an additional requirement of uniformity in the Y space direction is necessary. By Y space direction, it is meant coplanarity of the surfaces of the subunits making up the pagewidth scanning array. The prior art solutions to overcome this inability to provide cost effective pagewidth scanning arrays include optical and electrical arrangements for overlapping several short arrays and abutting short arrays together end-to-end. However, none of these attempts have met with any great degree of success. For example, in the case of abutting smaller arrays together, losses and distortions of the pagewidth image often occurs because of the inability to achieve exact alignment of the smaller arrays with respect to each other. Another important problem with simply abutting chips or subunits is that chip or subunit width errors accumulate over the length of the pagewidth array.
IBM Technical Disclosure Bulletin, Vol. 23, No. 5, Oct. 1980 to B. D. Martin et al, entitled "Chip Protective Coating", discloses a chip or wafer having solder balls on one surface thereon. This surface and the balls are coated with a polyimide layer, so that the polyimide around each solder ball serves to envelope it. A shaving operation removes the tops of the balls including the polyimide layer thereover and produces flats for electrical testing or connection.
U.S. Pat. No. 4,645,688 to Makino et al discloses a composition for coating material of a semiconductor which consists of principal elements of a semiconductor memory element, an encapsulating layer containing an inorganic material and an intermediate layer of a protective coating material.
U.S. Pat. Nos. 4,690,391; 4,712,018 and 4,735,671 to Stoffel et al disclose a method for fabricating long full width scanning arrays. Smaller arrays are assembled in abutting end-to-end relationship by an aligning tool having predisposed pin-like projections insertable in locating grooves in a surface of the smaller arrays. Vacuum ports in the aligning tool surface to draw the smaller arrays into tight face-to-face contact with the tool. A suitable base is then affixed to the aligned small arrays and the aligning tool withdrawn leaving a full width scanning array composed of a row of end-to-end abutted smaller arrays.